Flash memory is non-volatile, which means that it stores information on a semiconductor in a way that does not need power to maintain the information in the chip. Flash memory is based on the Floating-Gate Avalanche-Injection Metal Oxide Semiconductor (FAMOS transistor), which is essentially a Complimentary Metal Oxide Semiconductor (CMOS) Field Effect Transistor (FET) with an additional conductor suspended between the gate and source/drain terminals. Current flash memory devices are made in two forms: NOR flash and NAND flash. The names refer to the type of logic used in the storage cell array. Further, flash memory stores information in an array of transistors, called “cells,” each of which traditionally stores one or more bits of information.
A flash cell is similar to a standard MOSFET transistor, except that it has two gates instead of just one. One gate is the control gate (CG) like in other MOS transistors, but the second is a floating gate (FG) that is insulated all around by an oxide layer. The FG is between the CG and the substrate. Because the FG is isolated by its insulating oxide layer, any electrons placed on it get trapped there and thus store the information.
When electrons are trapped on the FG, they modify (partially cancel out) an electric field coming from the CG, which modifies the threshold voltage (Vt) of the cell. Thus, when the cell is “read” by placing a specific voltage on the CG, electrical current will either flow or not flow between the cell's source and drain connections, depending on the Vt of the cell. This presence or absence of current is sensed and translated into 1's and 0's, reproducing the stored data.
Programming efficiency in flash memory, which is defined as a ratio of transistor gate current to programming drain-source current, is an important factor in determining power consumption in flash memories. The programming efficiency of flash memory cells, which utilize hot-electron injection, has been enhanced by applying substrate bias.
Mechanisms of hot-electron injection in a floating gate transistor during a program operation are well known. The channel hot electron (CHE) component comes from energetic channel electrons which are accelerated by lateral electric fields along a channel of the floating gate transistor. A channel initiated secondary electron (CHISEL) component comes from energetic electrons which are generated by hole impact ionization in the substrate and accelerated by vertical electric fields. As such, a gate current (Ig) by hot-electron injection in program mode can be expressed as Ig=ICHE+ICHISEL.
Known techniques for writing electrons onto the floating gate are still very inefficient. The drain current is on the order of a million times the gate current, or only about one in every millionth electron flowing down the transistor channel is injected or results in an electron being injected onto the floating gate. This requires that a high drain current be used during writing and excessive power dissipation.
A different non-volatile memory, Nitrided Read Only Memory (NROM), utilizes inherent physical features of an oxide-nitride-oxide (ONO) gate dielectric and known mechanisms of program and erase operations to create two separate physical bits per cell. The NROM cell is based on localized charge trapping. The cell is an n-channel MOSFET device where the gate dielectric is replaced by an ONO stack. Two spatially separated narrow charge distributions are stored in the nitride layer above junction edges. The NROM cell is programmed by channel hot electron injection.
A NROM or SONOS flash memory device has a charge trapping layer between a control gate (CG) and a channel of a MOSFET.
Electrons are injected into the trapping layer in a program operation, whereas they are released during the erase operation. NROM memory components are gaining wide acceptance and usage in a wide variety of portable battery operated electronic equipment such as personal digital assistants, PDA's, cellular phones and cameras.
The SONOS or NROM memory devices have attracted much attention due to their advantages over the traditional floating-gate flash device, including lower programming voltage, better scalability, and improved cycling endurance. An advantage of the NROM cell is the negligible vertical retention loss due to inhibition of direct tunneling. Further, in floating gate technology the charge is stored in a conductive layer, and any minor oxide defect or oxide trapped charge under the gate might cause leakage and loss of all the stored charge. NROM technology, however, uses a nitride insulator as a retaining material, hence only a large defect in the oxide (comparable to the cell size) could degrade retention.
A BiMOS structure has been used to study the basic physical mechanisms of electron trapping in MOS gate oxides; see FIG. 1. The test structure 100 included a gate 110, a gate oxide layer 120, source 130 and drain 140. A buried bipolar emitter-base diode, regions 150 and 160, was used to inject electrons which were accelerated in a surface depletion region and injected into the gate oxide 120. Excess electrons were collected by reverse biasing the drain and/or surface regions.
There is a need for improved efficiency and reduced power consumption in programming a non-volatile memory cell.